The present invention relates to a logic circuit employing field effect transistors, and more particularly to an E/D type logic circuit whose input-output characteristics have a hysteresis.
The E/D type logic circuit comprises a depletion type field effect transistor used as a load transistor and an enhancement type field effect transistor provided as a signal input transistor or a driving transistor, and can derive as a high level output almost a power supply level without level reduction. Therefore, it has high utilization efficiency of a power supply voltage. Further, a high speed operation is achieved, because the depletion type load transistor has a fast rise of a current fed therethrough in response to its gate voltage. It is necessary in a logic circuit that an output signal changes abruptly when an input signal exceeds a threshold value of the logic circuit, and a noise margin should be large so that once an output state has been established, it is not changed by a minute potential change in the input signal which is caused by noise or the like. In order to make this noise margin large, it has been commonly practiced to provide the input-output characteristics of a logic circuit with a hysteresis.
Let us consider an inverter circuit as a simplified example of the logic circuit having a hysteresis characteristic. The inverter circuit has a depletion type MOS transistor as a load and a driving MOS transistor of an enhancement type connected in series with the load transistor. In order to give a hysteresis characteristic to the inverter circuit, an enhancement-type feedback transistor is connected in parallel to the driving transistor, with a signal produced by inverting an output signal of the inverter being applied to the gate of the feedback transistor.
In a semiconductor integrated circuit having a plurality of MOS transistors, a relative error in characteristics of transistors formed on the same semiconductor substrate through the same process is in general, very small. However, even among transistors formed according to the same design specification, those formed through different processes and those formed on different semiconductor substrates though through the same process, would be associated with a large relative error in characteristics.
For the foregoing reason, the above-described inverter circuit having a hysteresis characteristic, when formed as a semiconductor integrated circuit, cannot have a predetermined relation in characteristics, just as designed, between the enhancement-type driving transistor and the depletion type load transistor, because the enhancement type transistor and the depletion type transistor are formed through different process.
Consequently, the hysteresis characteristic has been also influenced by the fluctuations in the characteristics among the transistors, especially between the depletion type transistor and the enhancement type transistor, and hence it has been difficult to obtain a logic circuit having a desired hysteresis characteristic.